DBS: Distributed Benchmark System

Performance Evaluation HIPPI over ATM Part II

The controller chip of HIPPI-ATM code/decode machine are remade by NEC referred the result of 'HIPPI over ATM Part I'. Under the same condition, performance is improved. But when there are many data streams, those throughput will become unfair.

System Structure

Data sheet

  CPU             SGI ONYX，CHALLENGE
  OS              IRIX 5.3
  ATM Switch      NEC ATOMIS7
  HIPPI ATM Codec NEC ATOMIS2
  TCP Buffer Size 256000byte
  Message Size    8192byte
  Number of Send  10000
  Start Time      0.0s: ONYX(20) -> CHALLENGE(36)
                  1.0s: ONYX(12) -> CHALLENGE(36)
                  2.0s: ONYX(20) -> CHALLENGE(36)
                  3.0s: ONYX(12) -> CHALLENGE(36)

Sequence Number(Application Level)

It's fair!
Each Throughput and Total Throughput (Application Level)

Data sheet

  CPU             SGI ONYX，CHALLENGE
  OS              IRIX 5.3
  ATM Switch      NEC ATOMIS7
  HIPPI ATM Codec NEC ATOMIS2
  TCP Buffer Size 5126000byte
  Message Size    65536byte
  Number of Send  1000
  Start Time      0.0s: ONYX(20) -> CHALLENGE(36)
                  0.5s: ONYX(12) -> CHALLENGE(36)
                  1.0s: ONYX(20) -> CHALLENGE(36)
                  1.5s: ONYX(12) -> CHALLENGE(36)
                  2.0s: ONYX(20) -> CHALLENGE(36)
                  2.5s: ONYX(12) -> CHALLENGE(36)
                  3.0s: ONYX(20) -> CHALLENGE(36)
                  3.5s: ONYX(12) -> CHALLENGE(36)

Sequence Number(Application Level)
Each Throughput and Total Throughput (Application Level)

Some throughputs are terrible wrong. You can see some TCP data transmission stop for 5s. It's unfair! This is caused by wrong design of HIPPI/ATM code/decode controler that are tunned transferring only 4 data streams at the same time. referred to the result of ' HIPPI over ATM Part I '.